1. Field of the Invention
The present invention relates to a microprocessor including a peripheral I/O (Input/Output) having a control register for controlling internal operations and making a setting, and more particularly to a microprocessor preventing erroneous writing to a control register.
2. Description of the Background Art
FIG. 1 is a block diagram showing an example of a conventional microprocessor including a circuit for preventing erroneous writing to peripheral I/Os and control registers of the peripheral I/Os. The microprocessor includes a CPU (Central Processing Unit) 101, peripheral I/Os 105a and 105b, an address decoder 104 for decoding an address outputted to an address bus 102 and generating a peripheral I/O selection signal 109 for selecting a peripheral I/O, a register 110 for storing the addresses of the peripheral I/Os to which erroneous writing is prevented, a comparator 111 for comparing the address outputted to address bus 102 and an address stored in register 110, a NAND gate 112, and an AND gate 113.
Peripheral I/Os 105a and 105b have control register groups 151a and 151b, respectively. CPU 101 writes a predetermined value to control register group 151a or 151b, thereby controlling the operations of peripheral I/Os 105a and 105b. In the case where CPU 101 writes a value to control register group 151a or 151b, first, a peripheral I/O access request signal 106 is set to a high (H) level to notify address decoder 104 of an access to the peripheral I/O. Simultaneously, CPU 101 sets a write valid signal 107 to the H level indicating that writing is valid, and outputs the address of the control register to which a value is set to address bus 102.
When peripheral I/O access request signal 106 rises to H level, address decoder 104 receives and decodes the address output to address bus 102 and, according to the result of decoding of the address, validates peripheral I/O selection signal 109 for selecting peripheral I/O 105a or 105b. 
Since write valid signal 107 is valid, selected peripheral I/O 105a or 105b receives the address outputted to address bus 102 and data outputted to a data bus 103, and writes the data to the control register selected by the address. In such a manner, peripheral I/O 105a or 105b sets a value to its control register and performs operation.
In the case of inhibiting writing of data to the control register in peripheral I/O 105a or 105b, CPU 101 sets the address of the control register into register 110. Comparator 111 compares the address outputted to address bus 102 at the time of writing a value to the control register in peripheral I/O 105a or 105b with the address set in register 110 and, if the addresses coincide with each other, outputs an H level signal.
When the H level signal is outputted from comparator 111 and write valid signal 107 is at the H level (valid), NAND gate 112 outputs a low (L) level signal. At this time, AND gate 113 masks peripheral I/O access request signal 106 and outputs an L level signal to address decoder 104. As a result, address decoder 104 invalidates all of peripheral I/O selection signals 109, thereby canceling a write request to peripheral I/O 105a or 105b. 
In the conventional microprocessor, CPU 101 can freely write the address of the control register to which writing is inhibited into register 110. Consequently, when the data in register 110 is rewritten due to a bug in a program executed by CPU 101 or erroneous operation of CPU 101, inhibition of writing to the control register in the peripheral I/O is canceled, and it causes a problem that writing inhibition cannot be normally performed.